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| sense & control data sheet rev. 2.0, 2014-02 TLE5012B angle sensor gmr-based angle sensor
TLE5012B data sheet 2 rev. 2.0, 2014-02 TLE5012B data sheet 3 rev. 2.0, 2014-02 trademarks of infineon technologies ag aurix?, c166?, canpak?, ci pos?, cipurse?, econopac k?, coolmos?, coolset?, corecontrol?, crossav e?, dave?, di-pol?, easypim?, econobridge?, econodual?, econopim?, econopack?, eicedriver?, eupec?, fcos?, hitfet?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my-d?, novalithic?, optimos?, origa?, powercode?; primarion?, pr imepack?, primestack?, pr o-sil?, profet?, rasic?, reversave?, satric?, si eget?, sindrion?, sipmos?, smartl ewis?, solid flash?, tempfet?, thinq!?, trenchstop?, tricore?. other trademarks advance design system? (ads) of agilent te chnologies, amba?, arm?, multi-ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat-iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvc o, llc (visa holdings in c.). epcos? of epcos ag. flexgo? of microsoft corp oration. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission electrot echnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mipi? of mipi allianc e, inc. mips? of mips technologies, inc., u sa. murata? of murata manufacturing co., microwave office? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. openwave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of si rius satellite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of symbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. tektro nix? of tektronix inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilo g?, palladium? of cadence design systems, inc. vlynq? of texas instruments incorpor ated. vxworks?, wind river? of wind ri ver systems, inc. zetex? of diodes zetex limited. last trademarks update 2011-11-11 revision history page or item subjects (major changes since previous revision) rev. 2.0, 2014-02 all chapters revised TLE5012B table of contents data sheet 4 rev. 2.0, 2014-02 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1 internal power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2 oscillator and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.3 sd-adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.4 digital signal processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.5 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.6 safety features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 sensing principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3.1 input/output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3.2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3.3 gmr parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3.4 angle performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.5 autocalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3.6 signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3.7 clock supply (clk timing definition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.4.1 synchronous serial communication (ssc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.4.1.1 ssc timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.4.1.2 ssc data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4.2 pulse width modulation (pwm) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.4.3 short pwm code (spc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.4.3.1 unit time setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.4.3.2 master trigger pulse requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.4.3.3 checksum nibble details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.4.4 hall switch mode (hsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.4.5 incremental interface (iif) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.5 test mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.5.1 adc test vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.6 supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.6.1 internal supply voltage comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table of contents TLE5012B table of contents data sheet 5 rev. 2.0, 2014-02 4.6.2 v dd overvoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.6.3 gnd - off comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.6.4 v dd - off comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5 pre-configured derivates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.1 iif-type: e1000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.2 hsm-type: e3005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3 pwm-type: e5000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.4 pwm-type: e5020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.5 spc-type: e9000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1 package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.2 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.4 packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 TLE5012B list of figures data sheet 6 rev. 2.0, 2014-02 figure 1-1 pg-dso-8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2-1 TLE5012B block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2-2 sensitive bridges of the gmr sensor (not to scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2-3 ideal output of the gmr sensor bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2-4 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3-1 application circuit for TLE5012B with iif interface and ssc (using internal clk) . . . . . . . . . . . . . 15 figure 3-2 application circuit for TLE5012B with hs mode and ssc (using internal clk) . . . . . . . . . . . . . . . 15 figure 3-3 application circuit for TLE5012B with only pwm inte rface (using internal clk) . . . . . . . . . . . . . . 16 figure 3-4 application circuit for TLE5012B with only pwm inte rface (using internal clk) . . . . . . . . . . . . . . 16 figure 3-5 application circuit for TLE5012B with only spc interf ace (using internal clk) . . . . . . . . . . . . . . . 17 figure 3-6 ssc configuration in sensor-slave mode with push-pull outputs (high-speed application) . . . . . . 17 figure 3-7 ssc configuration in sensor-slave mode and open-dr ain (bus systems) . . . . . . . . . . . . . . . . . . . . 18 figure 4-1 allowed magnetic field range as function of junction temperature.. . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4-2 offset and amplitude definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4-3 additional angle error for temperature changes above 5 kelvin within 1.5 revolutions . . . . . . . . . 25 figure 4-4 signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 4-5 delay of sensor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 4-6 external clk timing definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 4-7 ssc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 4-8 ssc data transfer (data-read example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 4-9 ssc data transfer (data-write example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 4-10 ssc bit ordering (read example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 4-11 update of update registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 4-12 fast crc polynomial division circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 4-13 typical example of a pwm signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 4-14 spc frame example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 4-15 spc pause timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 4-16 spc master pulse timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 4-17 hall switch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 4-18 hs hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 4-19 incremental interface with a/b mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 4-20 incremental interface with step/direction mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 4-21 adc test vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 4-22 overvoltage comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 4-23 gnd - off comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 4-24 v dd - off comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 6-1 pg-dso-8 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 6-2 position of sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 6-3 footprint of pg-dso-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 6-4 tape and reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 list of figures TLE5012B list of tables data sheet 7 rev. 2.0, 2014-02 table 1-1 derivate ordering codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2-1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4-2 operating range and parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4-3 input voltage and output currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 4-4 driver strength characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 4-5 electrical parameters for 4.5 v < v dd < 5.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 4-6 electrical parameters for 3.0 v < v dd < 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 4-7 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 4-8 basic gmr parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 4-9 angle performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 4-10 signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 4-11 internal clock timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 4-12 external clock specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 4-13 ssc push-pull timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 4-14 ssc open-drain timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 4-15 structure of the command word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 4-16 structure of the safety word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 4-17 bit types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 4-18 pwm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 4-19 frame configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 4-20 structure of status nibble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 4-21 predivider setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 4-22 master pulse parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 4-23 hall switch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 4-24 incremental interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 4-25 adc test vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 4-26 test comparator threshold voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 6-1 package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 6-2 sensor ic placement tolerances in package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 list of tables TLE5012B product description data sheet 8 rev. 2.0, 2014-02 1 product description figure 1-1 pg-dso-8 package 1.1 overview the TLE5012B is a 360 angle sensor that detects the orientation of a magnetic fi eld. this is achieved by measuring sine and cosine angle components with monolithic i ntegrated giant magneto resistance (igmr) elements. these raw signals (sine and cosine) are digitally processed internally to calculate the angle orientation of the magnetic field (magnet). the TLE5012B is a pre-calibrated sensor. the calibration parameters are stored in laser fuses. at start-up the values of the fuses are written into flip-flops, where these values can be changed by the application-specific parameters. further precision of the angle measurement over a wide temperature range and a long lifetime can be improved by enabling an optional internal autocalibration algorithm. data communications are accomplished with a bi-directi onal synchronous serial communication (ssc) that is spi-compatible. the sensor configuration is stored in registers, which are accessible by the ssc interface. additionally four other interfaces are available with the TLE5012B: puls e-width-modulation (pwm) protocol, short-pwm-code (spc) protocol, hall s witch mode (hsm) and incremental interface (iif). these interfaces can be used in parallel with ssc or alone. pre-configured sensor derivates with different interface settings are available (see table 1-1 and chapter 5 ) online diagnostic functions are provided to ensure reliable operation. note: see chapter 5 for description of derivates. table 1-1 derivate ordering codes product type marking ordering code package TLE5012B e1000 012b1000 sp001166960 pg-dso-8 TLE5012B e3005 012b3005 sp001166964 pg-dso-8 TLE5012B e5000 012b5000 sp001166968 pg-dso-8 TLE5012B e5020 012b5020 sp001166972 pg-dso-8 TLE5012B e9000 012b9000 sp001166998 pg-dso-8 TLE5012B product description data sheet 9 rev. 2.0, 2014-02 1.2 features ? g iant m agneto r esistance (gmr)- based principle ? integrated magnetic field sensing for angle measurement ? 360 angle measurement with revolution counter and angle speed measurement ? two separate highly accurate single bit sd-adc ? 15 bit representation of absolute angle value on the output (resolution of 0.01) ? 16 bit representation of sine / cosine values on the interface ? max. 1.0 angle error over lifetime and temp erature-range with activated auto-calibration ? bi-directional ssc interface up to 8mbit/s ? supports safety integrity level (sil) with diagnostic functions and status information ? interfaces: ssc, pwm, incremental interface (iif), hall switch mode (hsm), short pwm code (spc, based on sent protocol de fined in sae j2716) ? output pins can be configured (programmed or pre-configured) as push-pull or open-drain ? bus mode operation of multiple sensors on one line is possible with ssc or spc interface in open-drain configuration ?0.25 m cmos technology ? automotive qualified: -40c to 150c (junction temperature) ? esd > 4kv (hbm) ? rohs compliant (pb-free package) ? halogen-free 1.3 application example the TLE5012B gmr-based angle sensor is designed for angu lar position sensing in automotive applications such as: ? electrical commutated moto r (e.g. used in electric power steering (eps)) ? rotary switches ? steering angle measurements ? general angular sensing TLE5012B functional description data sheet 10 rev. 2.0, 2014-02 2 functional description 2.1 block diagram figure 2-1 TLE5012B block diagram 2.2 functional block description 2.2.1 internal power supply the internal stages of the TLE5012B are supplied with several voltage regulators: ? gmr voltage regulator, vrg ? analog voltage regulator, vra ? digital voltage regulator, vrd (derived from vra) these regulators are directly connected to the supply voltage v dd . 2.2.2 oscillator and pll the digital clock of the TLE5012B is given by the phase- locked loop (pll), which is by default fed by an internal oscillator. in order to synchronize the TLE5012B with other ics in a system, the TLE5012B can be configured via vrg vra vrd TLE5012B v dd x gmr y gmr temp sd- adc sd- adc sd- adc digital signal processing unit cordic ccu ram ssc interface incremental if pwm hsm spc csq sck data ifa ifb gnd ifc osc pll ism fuses TLE5012B functional description data sheet 11 rev. 2.0, 2014-02 ssc interface to use an external clock signal supplied on th e ifc pin as source for the pll, instead of the internal clock. external clock mode is only available in pwm or spc interface configuration. 2.2.3 sd-adc the s igma- d elta a nalog- d igital- c onverters ( sd-adc ) transform the analog gmr voltages and temperature voltage into the digital domain. 2.2.4 digital signal processing unit the digital signal processing unit (dspu) contains the: ? i ntelligent s tate m achine ( ism ), which does error compensation of offs et, offset temperature drift, amplitude synchronicity and orthogonality of the raw signals from the gmr bridges, and performs additional features such as auto-calibration, prediction and angle speed calculation ? co ordinate r otation di gital c omputer ( cordic ), which contains the trigonometric function for angle calculation ? c apture c ompare u nit ( ccu ), which is used to generate the pwm and spc signals ? r andom a ccess m emory ( ram ), which contains the configuration registers ? laser fuses, which contain the calibration parameters for the error-compensation and the ic default configuration, which is loaded into the ram at startup 2.2.5 interfaces bi-directional communication with the TLE5012B is enab led by a three-wire ssc interface. in parallel to the ssc interface, one secondary interface can be selected, which is available on the ifa, ifb, ifc pins: ?pwm ? incremental interface ? hall switch mode ? short pwm code by using pre-configured derivates (see chapter 5 ), the TLE5012B can also be operated with the secondary interface only, without ssc communication. 2.2.6 safety features the TLE5012B offers a multiplic ity of safety features to support the safety integrity level (sil) and it is a pro- sil tm product. safety features are: ? test vectors switchable to adc input (activated via ssc interface) ? inversion or combination of filter in put streams (activated via ssc interface) ? data transmission check via 8-bit c yclic r edundancy c heck ( crc ) for ssc communcation and 4-bit crc nibble for spc interface ? built-in self-test (bist) routines for ism, cordic, ccu, adcs run at startup ? two independent active interfaces possible ? overvoltage and undervoltage detection disclaimer pro-sil? is a registered tradem ark of infineon technologies ag. the pro-sil? trademark designates infineon produ cts which contain sil supporting features. sil supporting features are intended to support the over all system design to reach the desired sil (according to iec61508) or a-sil (according to iso26262) le vel for the safety system with high efficiency. TLE5012B functional description data sheet 12 rev. 2.0, 2014-02 sil respectively a-sil certification for such a system has to be reached on system level by the system responsible at an accredite d certification authority. sil stands for safety integrity level (according to iec 61508) a-sil stands for automotive-safety integrity level (according to iso 26262) 2.3 sensing principle the giant magneto resistance (gmr) sensor is implemen ted using vertical integrat ion. this means that the gmr-sensitive areas are integrated ab ove the logic part of the TLE5012B device. these gmr elements change their resistance depending on the direction of the magnetic field. four individual gmr elements are connected to one wheatstone sensor bridge. these gmr elements sense one of two components of the applied magnetic field: ? x component, v x (cosine) or the ? y component, v y (sine) with this full-bridge st ructure the maximum gmr signal is available an d temperature effects cancel out each other. figure 2-2 sensitive bridges of the gmr sensor (not to scale) attention: due to the rotational placement inaccuracy of the sensor ic in the package, the sensors 0 position may deviate by up to 3 from the package edge direction indicated in figure 2-2 . in figure 2-2 , the arrows in the resistors represent the magnetic direction which is fixed in the reference layer. if the external magnetic field is parallel to the direction of th e reference layer, the resistance is minimal. if they are anti-parallel, resi stance is maximal. the output signal of each bridge is only unambiguous over 180 between two maxima. therefore two bridges are oriented orthogonally to each other to measure 360. with the trigonometric function arctan 2, the true 360 angle value is calc ulated out of the raw x and y signals from the sensor bridges. v dd gnd adc x + gmr resistors adc x -adc y +adc y - v x v y 0 n s 90 TLE5012B functional description data sheet 13 rev. 2.0, 2014-02 figure 2-3 ideal output of the gmr sensor bridges v angle 90 180 270 360 0 v x (cos) y component (sin) v y (sin) v y v x x component (cos) TLE5012B functional description data sheet 14 rev. 2.0, 2014-02 2.4 pin configuration figure 2-4 pin configuration (top view) 2.5 pin description table 2-1 pin description pin no. symbol in/out function 1ifc (clk / iif_idx / hs3) i/o interface c: external clock 1) / iif index / hall switch signal 3 1) external clock feature is not avai lable in iif or hsm interface mode 2 sck i ssc clock 3 csq i ssc chip select 4 data i/o ssc data 5ifa (iif_a / hs1 / pwm / spc) i/o interface a: iif phase a / hall switch signal 1 / pwm / spc output (input for spc trigger only) 6v dd - supply voltage 7gnd-ground 8ifb (iif_b / hs2) o interface b: iif phase b / hall switch signal 2 12 34 5 6 7 8 center of sensitive area TLE5012B application circuits data sheet 15 rev. 2.0, 2014-02 3 application circuits the application circuits in this ch apter show the various communication possibilities of the TLE5012B. the pin output mode configuration is device -specific and it can be either push -pull or open-drain. the bit ifab_od (register ifab, 0d h ) indicates the output mode for the ifa, ifb a nd ifc pins. the ssc pins are by default push- pull (bit ssc_od, register mod_3, 09 h ). figure 3-1 shows a basic block diagram of a TLE5012B with incremental interface and ssc configuration. the derivate TLE5012B - e1000 is by default configured with push-pull ifa (iif_a), ifb (iif_ b) and ifc (iif_idx) pins. figure 3-1 application circuit for TLE5012B with iif interface and ssc (using internal clk) in case that the ifa, ifb and ifc pins are configurated via the ssc interface as open-drain pins, three resistors (one for each line) between output line and v dd would be recommended (e.g. 2.2k ). figure 3-2 shows a basic block diagram of the TLE5012B wit h hs mode and ssc configuration. the derivate TLE5012B - e3005 is by default configurated with push-pull ifa (hs1), ifb (hs2) and ifc (hs3) pins. figure 3-2 application circuit for TLE5012B with hs mode and ssc (using internal clk) vrg vra vrd TLE5012B x gmr y gmr temp sd- adc sd- adc sd- adc ssc interface incremental if pwm hsm osc *) recommended , e.g . 100 ? 100 nf ifc (iif_idx) v dd (3.0 ? 5.5v) **) gnd pll csq sck data ifa (iif _a) ifb (iif _b) ssc iif **) r ecommended , e .g. 470 ? *) *) digital signal processing unit cordic ccu ram ism fuses vrg vra vrd TLE5012B x gmr y gmr temp sd- adc sd- adc sd- adc ssc interface incremental if pwm hsm osc *) recommended , e.g . 100 ? 100 nf ifc (hs3) v dd (3.0 ? 5.5v) **) gnd pll csq sck data ifa (hs1) ifb (hs2) ssc hsm **) recommended , e .g. 470 ? *) *) digital signal processing unit cordic ccu ram ism fuses TLE5012B application circuits data sheet 16 rev. 2.0, 2014-02 in case that the ifa, ifb and ifc pins are configurated via the ssc interface as open drain pins, three resistors (one for each line) between the output line and v dd would be recommended (e.g. 2.2k ). the TLE5012B can be configured with pwm only ( figure 3-3 ). the derivate TLE5012B - e5000 is by default configurated with push-pull ifa (pwm) pin. theref ore the following configuration is recommended: figure 3-3 application circuit for TLE5012B wi th only pwm interface (using internal clk) the TLE5012B - e5020 is also a pwm derivate but with o pen drain ifa (pwm) pin. a pull-up resistor (e.g. 2.2k ) should then be added between the ifa line and vdd, as shown in figure 3-4 . figure 3-4 application circuit for TLE5012B wi th only pwm interface (using internal clk) for safety reasons it is better that the non-used pins are connected to ground, rather than floating. a resistor between he data line pin and ground is recommended to avoid shortcuts if data generates any unexpected output. the csq line has to be connected to v dd to avoid unintentional activation of the ssc interface. vrg vra vrd TLE5012B x gmr y gmr temp sd- adc sd- adc sd- adc ssc interface incremental if pwm hsm osc *) recom mended , e .g. 10 .0k ? 100 nf ifc v dd (3.0 ? 5.5v) *) gnd pll csq sck data ifa (pwm) ifb digital signal processing unit cordic ccu ram ism fuses vrg vra vrd TLE5012B x gmr y gmr temp sd- adc sd- adc sd- adc ssc interface incremental if pwm hsm osc *) r ecom m ended , e.g . 2 .2k ? 100 nf ifc v dd (3.0 ? 5.5v) **) gnd pll csq sck data ifa (pwm) ifb **) recom m ended , e .g. 10 .0k ? *) digital signal processing unit cordic ccu ram ism fuses TLE5012B application circuits data sheet 17 rev. 2.0, 2014-02 the TLE5012B can be configured with spc only ( figure 3-5 ). this is only possible with the TLE5012B - e9000 derivate, which is by default configur ated with an open-drain ifa (spc) pin. figure 3-5 application circuit for TLE5012B with only spc interface (using internal clk) in figure 3-5 the ifc (s_nr[1]) and sck (s_nr[0]) pins are set to ground to generate the slave number (s_nr) 0 d (or 00 b ). for safety reasons it is better that the non-used pins are connected to ground , rather than floating. a resistor between the data line pin and ground is re commended to avoid shortcuts if data generates any unexpected output. the csq line has to be connected to v dd to avoid unintentional activation of the ssc interface. synchronous serial communication (ssc) configuration in figure 3-1 and figure 3-2 the ssc interface has the default pus h-pull configuration (see details in figure 3-6 ). series resistors on the data, sck (serial clock signal) and csq (chip select) lines are recommended to limit the current in the erroneous case that either the sensor pushes high and the microcontroller pulls low at the same time or vice versa. the resistors in the sck and csq lines are only necessary in case of disturbances or noise. figure 3-6 ssc configuration in sensor-slave mode with push-pull outputs (high-speed application) vrg vra vrd TLE5012B x gmr y gmr temp sd- adc sd- adc sd- adc ssc interface incremental if pwm hsm osc *) r ecommended , e.g . 2 .2k ? 100 nf ifc (s_nr[1]) v dd (3.0 ? 5.5v) **) gnd pll csq sck (s _nr[0]) data ifa (spc ) ifb **) r ecommended , e .g. 10 .0k ? *) digital signal processing unit cordic ccu ram ism fuses shift reg. shift reg. clock gen. data mtsr mrst sck sck (ssc slave) tle 5012b c (ssc master) csq csq **) *) *) en en *) optional , e.g . 100 ? **) optional , e.g . 470 ? TLE5012B application circuits data sheet 18 rev. 2.0, 2014-02 it is also possible to use an open-drain setup for the data, sck and csq lines. this setup is designed to communicate with a microcontroller in a bus system, togeth er with other ssc slaves (e.g. two TLE5012B devices for redundancy reasons). this mode can be activated using the bit ssc_od. the open-drain configuration can be seen in figure 3-7 . series resistors on the data, sck, and csq lines are recommended to limit the current in case either the microcon troller or the sensor are accidentally switched to push- pull. a pull-up resistor of typ. 1 k is required on the data line. figure 3-7 ssc configuration in sensor-slave mode and open-drain (bus systems) shift reg. shift reg. clock gen. data mrst mtsr sck sck (ssc slave) tle 5012b c (ssc master) csq csq *) *) *) *) typ. 1k ? *) optional , e.g . 100 ? TLE5012B specification data sheet 19 rev. 2.0, 2014-02 4 specification 4.1 absolute maximum ratings attention: stresses above the max. values listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the device. 4.2 operating range the following operating conditions must not be exceeded in order to ensure correct operation of the TLE5012B. all parameters specified in the followi ng sections refer to these operating conditions, unless otherwise noted. table 4-2 is valid for -40c < t j < 150c unless otherwise noted. table 4-1 absolute maximum ratings parameter symbol values unit note / test condition min. typ. max. voltage on v dd pin with respect to ground (v ss ) v dd -0.5 6.5 v max 40 h/lifetime voltage on any pin with respect to ground (v ss ) v in -0.5 6.5 v v dd + 0.5 v junction temperature t j -40 150 c 150 c for 1000 h, not additive magnetic field induction b 200 mt max. 5 min @ t a = 25c 150 mt max. 5 h @ t a = 25c storage temperature t st -40 150 c without magnetic field table 4-2 operating range and parameters parameter symbol values unit note / test condition min. typ. max. supply voltage v dd 3.0 5.0 5.5 v 1) supply current i dd 14 16 ma magnetic induction at t j = 25c 2)3) b xy 30 50 mt -40c < t j < 150c 30 60 mt -40c < t j < 100c 30 70 mt -40c < t j < 85c extended magnetic induction range at t j = 25c 2)3) b xy 25 30 mt additional angle error of 0.1 angle range ang 0 360 por level v por 2.0 2.9 v power-on reset por hysteresis v porhy 30 mv TLE5012B specification data sheet 20 rev. 2.0, 2014-02 the field strength of a magnet can be selected within the colored area of figure 4-1 . by limitation of the junction temperature, a higher magnetic field can be ap plied. in case of a maximum temperature t j =100c, a magnet with up to 60mt at t j = 25c is allowed. it is also possible to widen the magnetic field range for higher temperatures. in that case, additional angle errors have to be considered. figure 4-1 allowed magnetic field range as function of junction temperature. power-on time 4) t pon 57msv dd > v ddmin ; fast reset time 5) t rfast 0.5 ms fast reset is triggered by disabling startup bist (s_bist = 0), then enabling chip reset (as_rst = 1) 1) directly blocked with 100-nf ceramic capacitor 2) values refer to a homogeneous magnetic field (b xy ) without vertical magnetic induction (b z = 0mt). 3) see figure 4-1 4) during ?power-on time,? write access is not permitted (except fo r the switch to external clock which requires a readout as a confirmation that external clock is selected) 5) not subject to production test - ve rified by design/characterization table 4-2 operating range (cont?d) and parameters parameter symbol values unit note / test condition min. typ. max. TLE5012B specification data sheet 21 rev. 2.0, 2014-02 4.3 characteristics 4.3.1 input/output characteristics the indicated parameters apply to the full operating range, unless otherwise specified. the typical values correspond to a supply voltage v dd = 5.0 v and 25 c, unless individually specified. all other values correspond to -40 c < t j < 150c. within the register mod_3, the driver strength and th e slope for push-pull communication can be varied depending on the sensor output. the driv er strength is specified in table 4-3 and the slope fall and rise time in table 4-4 . table 4-3 input voltage and output currents parameter symbol values unit note / test condition min. typ. max. input voltage v in -0.3 5.5 v v dd + 0.3 v output current (data-pad) i q -25 ma pad_drv =?0x?, sink current 1)2) 1) max. current to gnd over open-drain output 2) at v dd = 5 v -5 ma pad_drv =?10?, sink current 1)2) -0.4 ma pad_drv =?11?, sink current 1)2) output current (ifa / ifb / ifc - pad) i q -15 ma pad_drv =?0x?, sink current 1)2) -5 ma pad_drv =?1x?, sink current 1)2) table 4-4 driver strength characteristic parameter symbol values unit note / test condition min. typ. max. output rise/fall time t fall , t rise 8 ns data, 50 pf, pad_drv=?00? 1)2) 1) valid for push-pull output 2) not subject to production test - ve rified by design/characterization 28 ns data, 50 pf, pad_drv=?01? 1)2) 45 ns data, 50 pf, pad_drv=?10? 1)2) 130 ns data, 50 pf, pad_drv=?11? 1)2) 15 ns ifa/ifb, 20 pf, pad_drv=?0x? 1)2) 30 ns ifa/ifb, 20 pf, pad_drv=?1x? 1)2) TLE5012B specification data sheet 22 rev. 2.0, 2014-02 table 4-5 electrical parameters for 4.5 v < v dd < 5.5 v parameter symbol values unit note / test condition min. typ. max. input signal low-level v l5 0.3 v dd v input signal high level v h5 0.7 v dd v output signal low-level v ol5 1v data; i q = -25 ma (pad_drv=?0x?), i q = -5 ma (pad_drv=?10?), i q = -0.4 ma (pad_drv=?11?) 1v ifa,b,c; i q = -15 ma (pad_drv=?0x?), i q = -5 ma (pad_drv=?1x?) pull-up current 1) 1) internal pull-ups on csq and data pin are always enabled. i pu -10 -225 acsq -10 -150 adata pull-down current 2) 2) internal pull-downs on ifa, ifb and ifc are enabled during startup and in open-drain mode, internal pull-down on sck is always enabled. i pd 10 225 asck 10 150 a ifa, ifb, ifc table 4-6 electrical parameters for 3.0 v < v dd < 3.6 v parameter symbol values unit note / test condition min. typ. max. input signal low-level v l3 0.3 v dd v input signal high level v h3 0.7 v dd v output signal low-level v ol3 0.9 v data; i q = -15 ma (pad_drv=?0x?), i q = -3 ma (pad_drv=?10?), i q = -0.24 ma (pad_drv=?11?) 0.9 v ifa,ifb; i q = - 10 ma (pad_drv=?0x?), i q = -3 ma (pad_drv=?1x?) pull-up current 1) 1) internal pull-ups on csq and data pin are always enabled. i pu -3 -225 acsq -3 -150 adata pull-down current 2) 2) internal pull-downs on ifa, ifb and ifc are enabled during startup and in open-drain mode, internal pull-down on sck is always enabled. i pd 3225 asck 3150 a ifa, ifb, ifc TLE5012B specification data sheet 23 rev. 2.0, 2014-02 4.3.2 esd protection 4.3.3 gmr parameters all parameters apply over b xy = 30mt and t a = 25c, unless otherwise specified. figure 4-2 offset and amplitude definition table 4-7 esd protection parameter symbol values unit notes min. max. esd voltage v hbm 4.0 kv human body model 1) 1) human body model (hbm) according to: aec-q100-002 v sdm 0.5 kv socketed device model 2) 2) socketed device model (sdm) accord ing to: esda/ansi/esd sp5.3.2-2008 table 4-8 basic gmr parameters parameter symbol values unit note / test condition min. typ. max. x, y output range rg adc 23230 digits operating range 1) 1) not subject to production test - ve rified by design/characterization x, y amplitude 2) 2) see figure 4-2 a x , a y 6000 9500 15781 digits at ambient temperature 3922 20620 digits operating range x, y synchronicity 3) 3) k = 100*(a x /a y ) k 87.5 100 112.49 % x, y offset 4) 4) o y =(y max + y min ) / 2; o x = (x max + x min ) / 2 o x , o y -2048 0 +2047 digits x, y orthogonality error ? -11.25 0 +11.24 x, y amplitude without magnet x 0 , y 0 +4096 digits operating range 1) angle 90 180 270 360 0 +a offset v y 0 -a TLE5012B specification data sheet 24 rev. 2.0, 2014-02 4.3.4 angle performance after internal calculation, the sensor has a remaining error, as shown in table 4-9 . the error value refers to b z = 0mt and the operating conditions given in table 4-2 ?operating range and parameters? on page 19 . the overall angle error represents the relative angle erro r. this error describes the deviation from the reference line after zero-angle definition. it is valid for a static magnetic field. if the magnetic field is rotating during the measuremen t, an additional propagation error is caused by the angle delay time (see table 4-10 ?signal processing? on page 27 ), which the sensor needs to calculate the angle from the raw sine and cosine values from the mr bridges. in fast-turning applications, prediction can be enabled to reduce this propagation error. if autocalibration (see chapter 4.3.5 ) is enabled and the temperature changes by more than 5 kelvin during 1.5 revolutions an additional error has to be added to the specified angle error in table 4-9 . this error depends on the temperature change (delta temperature) as well as fr om the initial temperature (tstart) as shown in figure 4-3 . once the temperature stabilizes and the application complete s 1.5 revolutions, then the angle error is as specified in table 4-9 . for negative delta temperature changes (from higher to lower temperatures) the addit ional angle error will be smaller than the corresponding positive delta temperatur e changes (from lower to higher temperatures) shown in figure 4-3 . the figure 4-3 applies to th e worst case. table 4-9 angle performance parameter symbol values unit note / test condition min. typ. max. overall angle error (with auto- calibration) err 0.6 1) 1) at 25c, b = 30mt 1.0 including lifetime and temperature drift 2)3)4) . note: in case of temperature changes above 5 kelvin within 1.5 revolutions refer to figure 4-3 for additional angle error. 2) including hysteresis error, caused by revolution direction change 3) relative error after zero angle definition 4) not subject to production test - ve rified by design/characterization overall angle error (without auto- calibration) err 0.6 1) 1.3 including temperature drift 2)3)5) 5) 0h 1.9 including lifetime and temperature drift 2)3)4) TLE5012B specification data sheet 25 rev. 2.0, 2014-02 figure 4-3 additional angle error for temperature ch anges above 5 kelvin within 1.5 revolutions 4.3.5 autocalibration the autocalibration enables online parameter calculation and therefore reduces the angle error due to temperature and lifetime drifts. the TLE5012B is a pre-calibrated sensor, so autocalibra tion is only enabled in some devices by default. the update mode can be chosen with th e autocal setting in the mod_2 re gister. the TLE5012B needs 1.5 revolutions to generate new autocalibration parameters . these parameters are co ntinuously updated. the parameters are updated in a smooth way (one least-signif icant bit within the chosen range or time) to avoid an angle jump on the output. autocal modes: ? 00: no autocalibration ? 01: autocalibration mode 1. one lsb to final values within the update time t upd (depending on fir_md setting). ? 10: autocalibration mode 2. only one lsb update over one full parameter generation (1.5 revolutions). after update of one lsb, the aut ocalibration will calculat e the parameters again. ? 11: autocalibration mode 3. one lsb to final values within an angle range of 11.25 0 0.5 1 1.5 2 2.5 3 3.5 0 102030405060708090100110120130140150160170180190 additional angle error () delta temperature (kelvin) within 1.5 revolutions tstart -40c tstart 25c tstart 85c tstart 105c tstart 125c tstart 135c tstart >135c TLE5012B specification data sheet 26 rev. 2.0, 2014-02 4.3.6 signal processing figure 4-4 signal path the signal path of the TLE5012B is depicted in figure 4-4 . it consists of the gmr-bridge, adc, filter and angle calculation. the delay time between a physical change in the gmr elemen ts and a signal on the output depends on the filter and interface configurations . in fast turning applications, this delay causes an additional rotation speed dependent angle error. the TLE5012B has an optional prediction feature, whic h serves to reduce the speed dependent angle error in applications where the rotation speed does not change abr uptly. prediction uses the difference between current and last two angle values to appr oximate the angle value which will be present after the delay time (see figure 4-5 ). the output value is calculated by adding this difference to the measured value, according to equation (4.1) . (4.1) figure 4-5 delay of sensor output x gmr y gmr sd- adc sd- adc angle calculation filter filter TLE5012B microcontroller if adeliif t delif t adelssc t ) 2 ( ) 1 ( ) ( ) 1 ( ? ? ? + = + t t t t d d d d time angle with prediction without prediction t adel t upd magnetic field direction sensor output TLE5012B specification data sheet 27 rev. 2.0, 2014-02 all delay times specified in table 4-10 are valid for an ideal internal oscilla tor frequency of 24 mhz. for the exact timing, the variation of the in ternal oscillator frequency has to be taken into account (see chapter 4.3.7 ) table 4-10 signal processing parameter symbol values unit note / test condition min. typ. max. filter update period t upd 42.7 s fir_md = 1 (default) 1) 1) not subject to production test - ve rified by design/characterization 85.3 sfir_md = 2 1) 170.6 sfir_md = 3 1) angle delay time without prediction 2) 2) valid at constant rotation speed t adelssc 85 95 sfir_md = 1 1) 150 165 sfir_md = 2 1) 275 300 sfir_md = 3 1) t adeliif 120 135 sfir_md = 1 1) 180 200 sfir_md = 2 1) 305 330 sfir_md = 3 1) angle delay time with prediction 2) t adelssc 45 50 s fir_md = 1; predict = 1 1) 65 70 s fir_md = 2; predict = 1 1) 105 115 s fir_md = 3; predict = 1 1) t adeliif 75 90 s fir_md = 1; predict = 1 1) 95 110 s fir_md = 2; predict = 1 1) 135 150 s fir_md = 3; predict = 1 1) angle noise (rms) n angle 0.08 fir_md = 1 1) 0.05 fir_md = 2 1) (default) 0.04 fir_md = 3 1) TLE5012B specification data sheet 28 rev. 2.0, 2014-02 4.3.7 clock supply (clk timing definition) the internal clock supply of the TLE5012B is subject to production-specific variations , which have to be considered for all timing specifications. in order to fix the ic timing and sync hronize the TLE5012B with other ics in a system, it can be switched to operate with an external clock signal suppli ed to the ifc pin. the clock input si gnal must fulfill cert ain requirements: ? the high or low pulse width must not exceed the s pecified values, because the pll needs a minimum pulse width and must be spike-filtered. ? the duty cycle factor should typically be 50%, but it can vary between 30% and 70%. ? the pll is triggered at the positive edge of the clock. if more than 2 edges are missing, a chip reset is generated automatically and the sensor restarts with the internal clock. this is in dicated by the s_rst, and clk_sel bits, and additionally by the safety word (see chapter 4.4.1.2 ). figure 4-6 external clk timing definition table 4-11 internal clock timing specification parameter symbol values unit note / test condition min. typ. max. digital clock f dig 22.8 24 25.8 mhz internal oscillator frequency f clk 3.8 4.0 4.3 mhz table 4-12 external cl ock specification parameter symbol values unit note / test condition min. typ. max. input frequency f clk 3.8 4.0 4.3 mhz clk duty cycle 1)2) 1) minimum duty cycle factor: t clkh(min) / t clk with t clk = 1 / f clk 2) maximum duty cycle factor: t clkh(max) / t clk with t clk = 1 / f clk clk duty 30 50 70 % clk rise time t clkr 30 ns from v l to v h clk fall time t clkf 30 ns from v h to v l t clkh t clkl t clk t v l v h TLE5012B specification data sheet 29 rev. 2.0, 2014-02 4.4 interfaces 4.4.1 synchronous serial communication (ssc) the 3-pin ssc interface consists of a bi-directional pu sh-pull (tri-state on receive) or open-drain data pin (configurable with ssc_od bit) and the serial clock and chip-select input pins. the ssc interface is designed to communicate with a microcontroller peer-to-peer for fast applications. 4.4.1.1 ssc timing definition figure 4-7 ssc timing ssc inactive time (cs off ) the ssc inactive time defines the de lay time after a transfer before the TLE5012B can be selected again. table 4-13 ssc push-pull timing specification parameter symbol values unit note / test condition min. typ. max. ssc baud rate f ssc 8.0 mbit/s 1) 1) not subject to production test - ve rified by design/characterization csq setup time t css 105 ns 1) csq hold time t csh 105 ns 1) csq off t csoff 600 ns ssc inactive time 1) sck period t sckp 120 125 ns 1) sck high t sckh 40 ns 1) sck low t sckl 30 ns 1) data setup time t datas 25 ns 1) data hold time t datah 40 ns 1) write read delay t wr_delay 130 ns 1) update time t csupdate 1 ssee figure 4-11 1) sck off t sckoff 170 ns 1) sck t css t sckp t sckh t csh csq t sckl t csoff t datas data t datah TLE5012B specification data sheet 30 rev. 2.0, 2014-02 table 4-14 ssc open-drain timing specification parameter symbol values unit note / test condition min. typ. max. ssc baud rate f ssc 2.0 mbit/s pull-up resistor = 1k ? 1) 1) not subject to production test - ve rified by design/characterization csq setup time t css 300 ns 1) csq hold time t csh 400 ns 1) csq off t csoff 600 ns ssc inactive time 1) sck period t sckp 500 ns 1) sck high t sckh 190 ns 1) sck low t sckl 190 ns 1) data setup time t datas 25 ns 1) data hold time t datah 40 ns 1) write read delay t wr_delay 130 ns 1) update time t csupdate 1 ssee figure 4-11 1) sck off t sckoff 170 ns 1) TLE5012B specification data sheet 31 rev. 2.0, 2014-02 4.4.1.2 ssc data transfer the ssc data transfer is word-aligned. the following transfer words are possible: ? command word (to access and change operating modes of the TLE5012B) ? data words (any data transferred in any direction) ? safety word (confirms the data transf er and provides status information) figure 4-8 ssc data transfer (data-read example) figure 4-9 ssc data transfer (data-write example) command word ssc communication between the TLE5012B and a microcontr oller is generally initiate d by a command word. the structure of the command word is shown in table 4-15 . if an update is trig gered by shortly pulling low csq without a clock on sck a snapshot of all syst em values is stored in the update r egisters simultaneously. a read command with the upd bit set then allows to readou t this consistent se t of values instead of the current values. bits with an update buffer are marked by an ?u? in the type column in register descriptions. the initialization of such an update is described on page 33 . table 4-15 structure of the command word name bits description rw [15] read - write 0: write 1: read lock [14..11] 4-bit lock value 0000 b : default operating access for addresses 0x00:0x04 1010 b : configuration access for addresses 0x05:0x11 command read data 1 read data 2 safety-word ssc-master is driving data ssc-slave is driving dat a t wr_delay command write data 1 safety-word ssc-master is driving data ssc-slave is driving dat a t wr_delay TLE5012B specification data sheet 32 rev. 2.0, 2014-02 safety word the safety word consists of the following bits: bit types the types of bits used in the registers are listed here: upd [10] update-register access 0: access to current values 1: access to values in update buffer addr [9..4] 6-bit address nd [3..0] 4-bit number of data words table 4-16 structure of the safety word name bits description stat 1) 1) when an error occurs, the corresponding status bit in the sa fety word remains ?low? until the stat register (address 00 h ) is read via ssc interface. chip and interface status [15] indication of chip reset or watchd og overflow (resets after readout) via ssc 0: reset occurred 1: no reset [14] system error (e.g. overvoltage; undervoltage; v dd -, gnd- off; rom;...) 0: error occurred (s_v r; s_dspu; s_ov; s_xyo l: s_magol; s_fuse; s_rom; s_adct) 1: no error [13] interface access error (access to wrong address; wrong lock) 0: error occurred 1: no error [12] valid angle value (no_gmr_a = 0; no_gmr_xy = 0) 0: angle value invalid 1: angle value valid resp [11..8] sensor number response indicator the sensor number bit is pulled low and the other bits are high crc [7..0] cyclic redundancy check (crc) table 4-17 bit types abbreviation function description r read read-only registers w write read and write registers u update update buffer for this bit is present. if an update is issued and the update- register access bit (upd in command wo rd) is set, the immediate values are stored in this update buffer simulta neously. this allows a snapshot of all necessary system parameters at the same time. table 4-15 structure of the command word (cont?d) name bits description TLE5012B specification data sheet 33 rev. 2.0, 2014-02 data communication via ssc figure 4-10 ssc bit ordering (read example) figure 4-11 update of update registers the data communication via ssc interface has the following characteristics: ? the data transmission order is most-significant bi t (msb) first, last-signi ficant bit (lsb) last. ? data is put on the data line with the rising edge on sck and read with the fa lling edge on sck. ? the ssc interface is word-aligned. all functions are activated after each transmitted word. ? after every data transfer with nd 1, the 16-bit safety word is appended by the TLE5012B. ? a ?high? condition on the chip select pin (csq) of the selected TLE5012B interrupts the transfer immediately. the crc calculator is automatically reset. ? after changing the data direction, a delay t wr_delay (see table 4-14 ) has to be implemented before continuing the data transfer. this is necessa ry for internal register access. ? if in the command word the number of data is greater than 1 (nd > 1), then a corresponding number of consecutive registers is read, star ting at the addres s given by addr. ? in case an overflow occurs at address 3f h , the transfer continues at address 00 h . ? if in the command word the number of data is zero ( nd = 0), the register at the address given by addr is read, but no safety word is sent by the tle501 2b. this allows a fast readout of one register. ? at a rising edge of csq without a prec eding data transfer (no sck pulse, see figure 4-11 ), the content of all registers which have an update buffer is saved into the buffer. this procedure serves to take a snapshot of all relevant sensor parameters at a given time. the content of the update buffer can then be read by sending a read command for the desired register and setting the upd bit of the command word to ?1?. ? after sending the safety word, the transfer ends. to start another data transfer, the csq has to be deselected once for at least t csoff . ? by default, the ssc interface is set to push-pull. the push -pull driver is active only if the TLE5012B has to send data, otherwise the data pin is set to high-impedance. sck data 8 11 10 9 msb 14 13 12 csq ssc transfer lsb 321 7 6 5 4 command w ord data word (s) ssc -m aster is dr iving dat a ssc -slave is driving dat a lsb 1 rw addr length lock msb t wr_delay upd sck data csq lsb lsb msb command w ord data word (s) update -signal update -event ssc -master is driving dat a ssc -slave is driving dat a t csupdate TLE5012B specification data sheet 34 rev. 2.0, 2014-02 cyclic redundancy check (crc) ? this crc is according to the j1850 bus specification. ? every new transfer rest arts the crc generation. ? every byte of a transfer will be ta ken into account to generate th e crc (also the sent command(s)). ? generator polynomial: x8+x4+x3+x2+1, but for the c rc generation the fast-crc gene ration circuit is used (see figure 4-12 ) ? the seed value of the fast crc circuit is ?11111111 b ?. ? the remainder is inverted before transmission. figure 4-12 fast crc polynomial division circuit 4.4.2 pulse width modulation (pwm) interface the pulse width modulation (pwm) interface can be selected via ssc (if_md = ?01?). the pwm update rate can be pr ogrammed within the register 0e h (ifab_res) in the following steps: ? ~0.25 khz with 12-bit resolution ? ~0.5 khz with 12-bit resolution ? ~1.0 khz with 12-bit resolution ? ~2.0 khz with 12-bit resolution pwm uses a square wave with constant frequency whose duty cycle is m odulated according to the last measured angle value (aval register). figure 4-13 shows the principal behavior of a pwm with vari ous duty cycles and the definition of timing values. the duty cycle of a pwm is defined by the following general formulas: (4.2) the duty cycle range between 0 - 6.25% and 93.75 - 100% is used only for diagnostic purposes. in case the sensor detects an error, the corresponding error bit in the status register is set and the pwm duty cycle goes to the lower (0 - 6.25%) or upper (93.75 - 100%) diagnostic range, depending on the kind of error (see ?output duty cycle range? in table 4-18 ). except for an s_adct error, an error is only indicated by the corresponding diagnostic duty-cycle as long as it persists, but at least once. however the value in the st atus register will remain until a read- out via the ssc interface or a chip reset is performed. an s_adct error on the other side will be transmitted until the next chip reset. this fail-safe diagnostic fu nction can be disabled via the mod_4 register. sensors with preset pwm are available as TLE5012B e50x0. xor x7 x6 x5 x4 x3 x2 xor x0 xor xor input serial crc output & tx_crc 1111 1 1 1 1 x1 parallel remainder pwm pwm off on pwm pwm on t f t t t t t cycle duty 1 = + = = TLE5012B specification data sheet 35 rev. 2.0, 2014-02 figure 4-13 typical example of a pwm signal the pwm frequency is derived from the digital clock via (4.3) the min/max values given in table 4-18 take into account th e internal digital clo ck variation specified in chapter 4.3.7 . if external clock is used, the variation of the pwm frequency can be derived from the variation of the external clock using equation (4.3) . table 4-18 pwm interface parameter symbol values unit note / test condition min. typ. max. pwm output frequencies (selectable by ifab_res) f pwm1 232 244 262 hz 1) 1) not subject to production test - ve rified by design/characterization f pwm2 464 488 525 hz 1) f pwm3 929 977 1050 hz 1) f pwm4 1855 1953 2099 hz 1) output duty cycle range dy pwm 6.25 93.75 % absolute angle 1) 2 % electrical error (s_rst; s_vr) 1) 98 % system error (s_fuse; s_ov; s_xyol; s_magol; s_adct) 1) 0 1 % short to gnd 1) 99 100 % short to v dd , power loss 1) t on ?0' t on = high level off = low level duty cycle = 6.25% duty cycle = 50% duty cycle = 93.75% t pwm t off vdd u ifa vdd u ifa t ?0' t vdd u ifa ?0' 4096 * 24 2 * ifab_res dig pwm f f = TLE5012B specification data sheet 36 rev. 2.0, 2014-02 4.4.3 short pwm code (spc) the short pwm code (spc) is a synchronized data tr ansmission based on the sen t protocol (single edge nibble transmission) defined by sae j2 716. as opposed to sent , which implies a contin uous transmission of data, the spc protocol transmits data only after receivin g a specific trigger pulse from the microcontroller. the required length of the trigger pulse depends on the sens or number, which is configurable. thereby, spc allows the operation of up to four sensors on one bus line. spc enables the use of enhanced protocol functionality du e to the ability to select between various sensor slaves (id selection). the slave number (s_nr) can be given by t he external circuit of sck and ifc pin. in case of v dd on sck, the s_nr[0] can be set to 1 and in the case of gnd on sck the s_nr[0] is equal to 0. s_nr[1] can be adjusted in the same way by the ifc pin. as in sent, the time between two cons ecutive falling edges defines the value of a 4-bit nibble, thus representing numbers between 0 and 15. the transmission time theref ore depends on the transmitted data values. the single edge is defined by a 3 unit time (ut, see chapter 4.4.3.1 ) low pulse on the output, followed by the high time defined in the protocol (nom inal values, may vary depending on the to lerance of the inter nal oscillator and the influence of external circuitry). all values are multiples of a unit time frame concept. a transfer consists of the following parts ( figure 4-14 ): ? a trigger pulse by the master, wh ich initiates the data transmission ? a synchronization period of 56 ut (in parallel, a new samp le is calculated) ? a status nibble of 12-27 ut ? between 3 and 6 data nibbles of 12-27 ut ? a crc nibble of 12-27 ut ? an end pulse to terminate the spc transmission figure 4-14 spc frame example the crc checksum includes the status nibble and the data nibbles, and can be used to check the validity of the decoded data. the sensor is availa ble for the next trigger pulse 90 s after the falling edge of the end pulse (see figure 4-15 ). figure 4-15 spc pause timing diagram in spc mode, the sensor does not continuously calcul ate an angle from the raw data. instead, the angle calculation is start ed by the trigger nibble from th e master. in this mode , the aval register, wh ich stores the angle value and can be read via ssc, contains the angle whic h was calculated after the last spc trigger nibble. synchronisation frame status -nibble data - nibble 1 bit 11 -8 data -nibble 2 bit 7 -4 data - nibble 3 bit 3-0 crc 56 tck 12 ..27 tck 12 .. 27 tck 12 .. 27 tck 12..27 tck 12 ..27 tck nibble- encoding : ( 12 +x) *tck tim e-base : 1 tck ( 3s+ /-dtck ) tr igger nibble end -pulse 24 ,34 ,51,78 tck 12 tck c activity sensor activity synchronisation fr ame ... trigger nibble end - pulse c activity sensor activity synchronisation fram e ... tr igger nibble > 90 s end -pulse TLE5012B specification data sheet 37 rev. 2.0, 2014-02 in parallel to spc, the ssc interface can be used for individual configuration. the number of transmitted spc nibbles can be changed to customize the amount of info rmation sent by the sensor. the frame contains a 16-bit angle value and an 8-bit temperature value in the full configuration ( table 4-19 ). sensors with preset spc are available as TLE5012B e9000 the status nibble, which is sent with each spc data frame, provides an error indication similar to the safety word of the ssc protocol. in case the sensor detects an error, the corresponding error bit in the status register is set and either the bit sys_err or the bit elec_err of the stat us nibble will be ?high?, depen ding on the kind of error (see table 4-20 ). except for an s_adct error, an error is only indicated by the corresponding error bit in the status nibble as long as it persists, but at least once. however the value in the status register will remain until a read-out via the ssc interface or a chip reset is performed. an s_adct erro r on the other side will be transmitted until the next chip reset. the fail-safe diagnostic function can be disabled via the mod_4 register. 4.4.3.1 unit time setup the basic spc protocol unit time granularity is defined as 3 s. every timing is a multiple of this basic time unit.to achieve more flexibility, trimming of th e unit time can be done within ifab_h yst. this enables a setup of different unit times. table 4-19 frame configuration frame type ifab_res data nibbles 12-bit angle 00 3 nibbles 16-bit angle 01 4 nibbles 12-bit angle, 8-bit temperature 10 5 nibbles 16-bit angle, 8-bit temperature 11 6 nibbles table 4-20 structure of status nibble name bits description sys_err [3] indication of system error (s _fuse, s_ov, s_xyol, s_magol, s_adct) 0: no system error 1: system error occurred elec_err [2] indication of electrical error (s_rst, s_vr) 0: no electrical error 1: electrical error occurred s_nr [1] slave number bit 1 (level on ifc) [0] slave number bit 0 (level on sck) table 4-21 predivider setting parameter symbol values unit note / test condition min. typ. max. unit time t unit 3.0 s ifab_hyst = 00 1) 1) not subject to production test - ve rified by design/characterization 2.5 ifab_hyst = 01 1) 2.0 ifab_hyst = 10 1) 1.5 ifab_hyst = 11 1) TLE5012B specification data sheet 38 rev. 2.0, 2014-02 4.4.3.2 master trigger pulse requirements an spc transmission is initia ted by a master trigger pulse on the ifa pin. to detect a low-level on the ifa pin, the voltage must be below a threshold v th . the sensor detects that the ifa line has been released as soon as v th is crossed. figure 4-16 shows the timing definitions for the master pulse. the master low time t mlow as well as the total trigger time t mtr are given in table 4-22 . if the master low time exceeds the maximum low time, the sensor does not respond and is available for a next triggering 30 s after the master pulse crosses v thr . t md,tot is the delay between internal triggering of the falling edge in the sensor and the triggering of the ecu. figure 4-16 spc master pulse timing 4.4.3.3 checksum nibble details the checksum nibble is a 4-bit crc of the data nibbles in cluding the status nibble. the crc is calculated using a polynomial x 4 +x 3 +x 2 +1 with a seed value of 0101 b . the remainder after the last data nibble is transmitted as crc. table 4-22 master pulse parameters parameter symbol values unit note / test condition min. typ. max. threshold v th 50 % of v dd 1) 1) not subject to production test - ve rified by design/characterization threshold hysteresis v thhyst 8% ofv dd = 5 v 1) 3v dd v dd = 3 v 1) total trigger time t mtr 90 ut spc_trigger = 0; 1)2) 2) trigger time in the sensor is fixed to the number of units sp ecified in the ?typ.? column, but the effective trigger time var ies due to the sensor?s clock variation t mlow +12 ut sp_trigger = 1 1) master low time t mlow 8 12 14 ut s_nr =00 1) 16 22 27 s_nr =01 1) 29 39 48 s_nr =10 1) 50 66 81 s_nr =11 1) master delay time t md,tot 5.8 s 1) spc ecu trigger level v th t mlow t md,tot t mtr TLE5012B specification data sheet 39 rev. 2.0, 2014-02 4.4.4 hall switch mode (hsm) the h all s witch m ode ( hsm ) within the TLE5012B makes it possible to emulate the output of 3 hall switches. hall switches are often used in electrical commutated motors to determine the rotor position. with these 3 output signals, the motor will be commuta ted in the right way. depending on which pole pairs of the ro tor are used, various electrical periods have to be cont rolled. this is selectable within 0e h (hsm_plp). figure 4-17 depicts the three output signals with the relationship between electrical angle and mechanical angle. the mechanical 0 point is always used as reference. the hsm is generally used with push-pull output, but it c an be changed to open-drain within the register ifab_od. sensors with preset hsm are available as TLE5012B e3005. figure 4-17 hall switch mode the hsm interface can be selected via ssc (if_md = 010). table 4-23 hall switch mode parameter symbol values unit note / test condition min. typ. max. rotation speed n 10000 rpm mechanical 2) hs1 hs2 hs3 0 electrical angle 60 120 180 240 300 360 hall-switch-mode: 3phase generation angle mech. angle with 5 pole pairs 0 12 24 36 48 60 72 0 20 40 60 80 100 120 mech. angle with 3 pole pairs TLE5012B specification data sheet 40 rev. 2.0, 2014-02 electrical angle accuracy elect 0.6 1 1 pole pair with autocalibration 1)2) 1.2 2 2 pole pairs with autocal. 1)2) 1.8 3 3 pole pairs with autocal. 1)2) 2.4 4 4 pole pairs with autocal. 1)2) 3.0 5 5 pole pairs with autocal. 1)2) 3.6 6 6 pole pairs with autocal. 1)2) 4.2 7 7 pole pairs with autocal. 1)2) 4.8 8 8 pole pairs with autocal. 1)2) 5.4 9 9 pole pairs with autocal. 1)2) 6.0 10 10 pole pairs with autocal. 1)2) 6.6 11 11 pole pairs with autocal. 1)2) 7.2 12 12 pole pairs with autocal. 1)2) 7.8 13 13 pole pairs with autocal. 1)2) 8.4 14 14 pole pairs with autocal. 1)2) 9.0 15 15 pole pairs with autocal. 1)2) 9.6 16 16 pole pairs with autocal. 1)2) mechanical angle switching hysteresis hshystm 0 0.703 selectable by ifab_hyst 2)3)4) table 4-23 hall switch mode (cont?d) parameter symbol values unit note / test condition min. typ. max. TLE5012B specification data sheet 41 rev. 2.0, 2014-02 to avoid switching due to mechanical vibrations of the rotor, an artificial hysteresis is recommended ( figure 4-18 ). electrical angle switching hysteresis 5) hshystel 0.70 1 pole pair; ifab_hyst=11 1)2) 1.41 2 pole pairs; ifab_hyst=11 1)2) 2.11 3 pole pairs; ifab_hyst=11 1)2) 2.81 4 pole pairs; ifab_hyst=11 1)2) 3.52 5 pole pairs; ifab_hyst=11 1)2) 4.22 6 pole pairs; ifab_hyst=11 1)2) 4.92 7 pole pairs; ifab_hyst=11 1)2) 5.62 8 pole pairs; ifab_hyst=11 1)2) 6.33 9 pole pairs; ifab_hyst=11 1)2) 7.03 10 pole pairs; ifab_hyst=11 1)2) 7.73 11 pole pairs; ifab_hyst=11 1)2) 8.44 12 pole pairs; ifab_hyst=11 1)2) 9.14 13 pole pairs; ifab_hyst=11 1)2) 9.84 14 pole pairs; ifab_hyst=11 1)2) 10.55 15 pole pairs; ifab_hyst=11 1)2) 11.25 16 pole pairs; ifab_hyst=11 1)2) fall time t hsfall 0.02 1 sr l = 2.2k ? ; c l < 50pf 2) rise time t hsrise 0.4 1 sr l = 2.2k ? ; c l < 50pf 2) 1) depends on internal oscillator frequency variation ( section 4.3.7 ) 2) not subject to production test - ve rified by design/characterization 3) gmr hysteresis not considered 4) minimum hysteresis without switching 5) the hysteresis has to be considered only at change of rotation direction table 4-23 hall switch mode (cont?d) parameter symbol values unit note / test condition min. typ. max. TLE5012B specification data sheet 42 rev. 2.0, 2014-02 figure 4-18 hs hysteresis 4.4.5 incremental interface (iif) the i ncremental i nter f ace ( iif ) emulates the operation of an optical quadrature encoder with a 50% duty cycle. it transmits a square pulse per angle step, where the width of the steps can be configured from 9bit (512 steps per full rotation) to 12bit (4096 steps per full rotation) within the register mod_4 (ifab_res). the rotation direction is given either by the phase shift between the two channels ifa and ifb (a/b mode) or by the level of the ifb channel (step/direction mode), as shown in figure 4-19 and figure 4-20 . the incremental interface can be configured for a/b mode or step/direction mode in register mod_1 (iif_mod). using the incremental interface requires an up/down counter on the microcontroller, which counts the pulses and thus keeps track of the absolute position. the counter ca n be synchronized periodically by using the ssc interface in parallel. the angle value (aval register) read out by the ssc interface can be compared to the stored counter value. in case of a non-syn chronization, the microcontroller adds the difference to the actual counter value to synchronize the TLE5012B with the microcontroller. after startup, the iif transmits a number of pulses which correspond to the actual absolute angle value. thus, the microcontroller gets the information about the absolute po sition. the index signal that indicates the zero crossing is available on the ifc pin. sensors with preset iif are av ailable as TLE5012B e1000. a/b mode the phase shift between phases a and b indicates either a clockwise (a follows b) or a counterclockwise (b follows a) rotation of the magnet. figure 4-19 incremental interface with a/b mode ideal switching point elect hshystel hshystel elect 0 90 el . phase shift 0 1 2 3 4 5 6 7 6 5 4 3 2 1 phase a counter phase b incremental interface (a/b mode) v h v l v h v l TLE5012B specification data sheet 43 rev. 2.0, 2014-02 step/direction mode phase a pulses out the increments and phase b indicates the direction. figure 4-20 incremental interface with step/direction mode 4.5 test mechanisms 4.5.1 adc test vectors in order to test the correct functionality of the adcs, the adc inputs can be switched from the gmr bridge outputs to a chain of fixed resitors which act as a voltage divider. the adcs are then fed with te st vectors of fixed voltages to simulate a set of magnet positions. the functionality of the adcs is verified by checking the angle value (aval register) for each test vector. this test is activa ted via ssc command within the sil register (adctv_en). registers adctv_y and adctv_x are used to select the test vector, as shown in figure 4-21 . the following x/y adc values can be programmed: ? 4 points, circle amplitude = 70% (0,90, 180, 270) ? 8 points, circle amplitude = 100% (0, 45, 90, 135, 180, 225, 270, 315) ? 8 points, circle amplitude = 122.1% (35.3, 54.7, 125.3, 144.7, 215.3, 234.7, 305.3, 324.7) ? 4 points, circle amplitude = 141.4% (45, 135, 225, 315) note: the 100% values typically correspond to 21700 digits and the 70% values to 15500 digits. table 4-24 incremental interface parameter symbol values unit note / test condition min. typ. max. incremental output frequency f inc 1.0 mhz frequency of phase a and phase b 1) 1) not subject to production test - ve rified by design/characterization index pulse width t 0 5 s0 1) table 4-25 adc test vectors register bits x/y values (decimal) min. typ. max. 000 0 001 15500 010 21700 011 32767 100 1) 0 101 -15500 step counter direction incremental interface (step /direction mode) v h v l v h v l 0 1 2 3 4 5 6 7 6 5 4 3 2 1 TLE5012B specification data sheet 44 rev. 2.0, 2014-02 figure 4-21 adc test vectors 4.6 supply monitoring the internal voltage nodes of the TLE5012B are monitore d by a set of comparators in order to ensure error-free operation. an over- or undervoltage condition must be acti ve at least 256 periods of the digital clock to set the corresponding error bits in the status regist er. this works as digital spike suppression. over- or undervoltage errors trigger the s_vr bit of status register. this error condition is signaled via the in the safety word of the ssc protocol, the status nibble of th e spc interface or the lower diagnostic range of the pwm interface. 110 -21700 111 -32768 1) not allowed to use table 4-26 test comparator threshold voltages parameter symbol values unit note / test condition min. typ. max. overvoltage detection v ovg 2.80 v 1) 1) not subject to production test - ve rified by design/characterization v ova 2.80 v 1) v ovd 2.80 v 1) v dd overvoltage v ddov 6.05 v 1) v dd undervoltage v dduv 2.70 v 1) gnd - off voltage v gndoff -0.55 v 1) v dd - off voltage v vddoff 0.55 v 1) spike filter delay t del 10 s 1) table 4-25 adc test vectors (cont?d) register bits x/y values (decimal) min. typ. max. adctv_x adctv_y 0% 122.1% 100 .0% 70% 141.4% TLE5012B specification data sheet 45 rev. 2.0, 2014-02 4.6.1 internal supply voltage comparators every voltage regulator has an overvoltage (ov) comparator to detect malfunctions. if the nominal output voltage of 2.5 v is larger than v ovg , v ova and v ovd , then this overvoltage comparator is activated. 4.6.2 v dd overvoltage detection the overvoltage detection comparator monitors the external supply voltage at the v dd pin. figure 4-22 overvoltage comparator 4.6.3 gnd - off comparator the gnd - off comparator is used to detect a voltage di fference between the gnd pin and sck. this circuit can detect a disconnection of the supply gnd pin. figure 4-23 gnd - off comparator 4.6.4 v dd - off comparator the v dd - off comparator detects a disconnection of the vdd pin supply voltage. in this case, the TLE5012B is supplied by the sck and csq input pins via the esd structures. figure 4-24 v dd - off comparator ref - + 10s spike filter xxx_ov v dda gnd gnd v dd v rg v ra v rd - + 10s spike filter gnd_off v dda gnd sck gnd v dd +dv diode- reference 1s mono flop 10s spike filter vdd _off v dda gnd v dd csq sck -dv gnd 1s mono flop - + v vddoff TLE5012B pre-configured derivates data sheet 46 rev. 2.0, 2014-02 5 pre-configured derivates derivates of the 5012b are available with different pre-co nfigured register settings for specific applications. the configuration of all derivates can be changed via ssc interface. 5.1 iif-type: e1000 the TLE5012B-e1000 is preconfigured for incremental interface and fast angle update period (42.7 s). it is most suitable for bldc motor commutation. ? autocalibration mode 1 enabled. ? prediction enabled. ? hysteresis is set to 0.703. ? 12bit mode, one count per 0.088 angle step. ? incremental interface a/b mode. 5.2 hsm-type: e3005 the TLE5012B-e3005 is preconfigured for hall- switch-mode and fast angle update period (42.7 s). it is most suitable as a replacement for three ha ll switches for bldc motor commutation. ? number of pole pairs is set to 5. ? autocalibration mode 1 enabled. ? prediction enabled. ? hysteresis is set to 0.703. 5.3 pwm-type: e5000 the TLE5012B-e5000 is preconfigured for pulse-width-modulat ion interface. it is most suitable for steering angle and actuator position sensing. ? filter update period is 85.4 s. ? pwm frequency is 244 hz. ? autocalibration, prediction, and hysteresis are disabled. 5.4 pwm-type: e5020 the TLE5012B-e5020 is preconfigured for pulse-width-mo dulation interface with high frequency. it is most suitable for steering angle a nd actuator position sensing. ? filter update period is 42.7 s. ? pwm frequency is 1953 hz. ? autocalibration mode 2 enabled. ? prediction and hysteresis are disabled. ? pwm interface is set to open-drain output. 5.5 spc-type: e9000 the TLE5012B-e9000 is preconfigured for short-pwm-code interface. it is most suitable for steering angle and actuator position sensing. ? filter update period is 85.4 s. ? autocalibration, prediction, and hysteresis are disabled. ? spc unit time is 3 s. ? spc interface is set to open-drain output. TLE5012B package information data sheet 47 rev. 2.0, 2014-02 6 package information 6.1 package parameters 6.2 package outline figure 6-1 pg-dso-8 package dimension table 6-1 package parameters parameter symbol limit values unit notes min. typ. max. thermal resistance r thja 150 200 k/w junction to air 1) 1) according to jedec jesd51-7 r thjc 75 k/w junction to case r thjl 85 k/w junction to lead soldering moisture level msl 3 260c lead frame cu plating sn 100% > 7 m TLE5012B package information data sheet 48 rev. 2.0, 2014-02 figure 6-2 position of sensing element 6.3 footprint figure 6-3 footprint of pg-dso-8 table 6-2 sensor ic placement tolerances in package parameter values unit notes min. max. position eccentricity -200 200 m in x- and y-direction rotation -3 3 affects zero po sition offset of sensor tilt -3 3 0.65 1.31 5.69 1.27 TLE5012B package information data sheet 49 rev. 2.0, 2014-02 6.4 packing figure 6-4 tape and reel 6.5 marking processing note: for processing recommendations, please refer to infineon?s notes on processing position marking description 1st line 012bxxxx see ordering table on page 8 2nd line xxx lot code 3rd line gxxxx g..green, 4-digit..date code 8 6.4 5.2 0.3 0.3 12 2.1 1.75 published by infineon technologies ag www.infineon.com |
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